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Design Rule Verification Report

Date : 9/13/2016
Time : 3:25:12 PM
Elapsed Time : 00:00:01
Filename : D:\Personal\Synergy Technologies\Jenex Technologies\Blackbox\HW\4 layer_NEW_SIC\SIC_CC430.PcbDoc
Warnings : 0
Rule Violations : 8

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 4
Un-Routed Net Constraint ( (All) ) 0
Clearance Constraint (Gap=0.15mm) (All),(All) 4
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Width Constraint (Min=0.15mm) (Max=2mm) (Preferred=0.2mm) (All) 0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Hole Size Constraint (Min=0.25mm) (Max=3mm) (All) 0
Hole To Hole Clearance (Gap=0.15mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
SMD Neck-Down Constraint (Percent=400%) (All) 0
Length Constraint (Min=0mm) (Max=10mm) (InNet('RF_N') Or InNet('RF_P')) 0
Total 8

Short-Circuit Constraint (Allowed=No) (All),(All)
Via (26.888mm,31.314mm) Top Layer to Bottom Layer Pad U4-0(26.888mm,29.814mm) Multi-Layer
Via (26.888mm,28.339mm) Top Layer to Bottom Layer Pad U4-0(26.888mm,29.814mm) Multi-Layer
Region (0 hole(s)) Bottom Layer Via (26.888mm,28.339mm) Top Layer to Bottom Layer
Region (0 hole(s)) Bottom Layer Via (26.888mm,31.314mm) Top Layer to Bottom Layer
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Clearance Constraint (Gap=0.15mm) (All),(All)
Via (26.888mm,31.314mm) Top Layer to Bottom Layer Pad U4-0(26.888mm,29.814mm) Multi-Layer
Via (26.888mm,28.339mm) Top Layer to Bottom Layer Pad U4-0(26.888mm,29.814mm) Multi-Layer
Region (0 hole(s)) Bottom Layer Via (26.888mm,28.339mm) Top Layer to Bottom Layer
Region (0 hole(s)) Bottom Layer Via (26.888mm,31.314mm) Top Layer to Bottom Layer
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